Two port voltage controlled oscillator for use in wireless personal area network synthesizers

ABSTRACT

A voltage controlled oscillator (VCO) for use in a personal area network synthesizer includes a delay cell ( 100 ), a first current amplifier ( 201, 203 ) for amplifying an input current, a resister capacitor (RC) tuning network ( 207, 209, 211 ) for varying the amount of amplification and delay of an output of the first current amplifier. A second current amplifier ( 213, 215 ) is then used for amplifying an output current from the RC tuning network. The invention includes a unique composite voltage variable capacitor (CVVC) ( 300 ) for precisely tuning the amount of delay presented by the delay cell. The unique topology of the delay cell ( 100 ) allows it to be readily used in voltage controlled oscillators (VCOs) operable at frequencies above 1 GHz.

TECHNICAL FIELD

This invention relates in general to radio frequency synthesizers andmore particularly to a voltage controlled oscillator (VCO) topologyoperable above 1 GHz.

BACKGROUND

Wireless personal area networks (WPAN) are those networks generally usedfor interconnecting devices centered around people where the connectionsare wireless. Because most personal area networks are wireless, theacronym WPAN and the term “wireless network” often are considered to bevirtually synonymous. Generally, a wireless personal area network usestechnology that permits communication over a very short range, typically10 meters or less. One common example of this technology is 802.15.4,which is a standard developed by the Institute of Electrical andElectronics Engineers (IEEE).

As is well known in the art, a WPAN can serve to interconnect all theordinary personal computing and communicating devices that many peoplecarry with them today. Moreover, WPAN can also serve a more specializedpurpose such as allowing a surgeon and other medical team members tocommunicate during an operation. A key concept in WPAN technology isknown as “plugging-in.” In the ideal scenario, when any twoWPAN-equipped devices come into close proximity (within several metersof each other) or within a few kilometers of a central server, they cancommunicate as if connected through a wired connection. Still anotherimportant feature of WPAN is the ability of each device to selectivelylock out other devices, preventing unwanted interference or unauthorizedaccess to information.

Currently, technology for WPAN devices and systems is in its infancy andis undergoing rapid development with a proposed operating frequency atapproximately 2.4 GHz in digital modes. The ultimate objective of thistechnology is to facilitate seamless operation among home or businessdevices and their networking systems. In an ideal scenario, every devicein a WPAN shall be able to plug in to any other device in the same WPAN,provided they are within physical range of one another. In addition,WPANs worldwide shall be interconnected. As one example, an archeologiston site in Greece might use a personal digital assistant (PDA) todirectly access databases at the University of Michigan in Ann Arbor,Mich., and to transmit findings to that database.

Radio frequency (RF) technology enabling WPAN-equipped devices tointerconnect can be very complex. Operation at frequencies at and above1 GHz requires specialized RF circuit topologies for fast and reliableoperation. One such circuit topology that can present a problem at thesefrequencies is the voltage controlled oscillator or “VCO.” As seen inprior art FIG. 1, a block diagram of the VCO typically is arranged in aloop configuration where a series of delay cells are used to offer bothgain and phase delay. As is well known by those skilled in the art, thistype of configuration is also commonly referred to as a “ringoscillator.” The delay cells are used to provide both in-phase (I) andquadrature (Q) digital output signals at some time later than the inputsignal applied to the VCO. The output signal is inverted and fed back tothe input of the delay cells. This in turn causes the circuit tooscillate in view of a 180 degree phase shift between input and output.

The topology of the VCO delay cell has offered interesting challengeswhen requiring it to operate at frequencies above 1 GHz. Prior art FIGS.2 and 3 illustrate both a current starved ring oscillator delay cell anda non-linear resistive capacitive (RC) type delay cell. Both of thesetypes of circuit topologies operate in a voltage mode controlled by thevoltage gain (G_(m)) of the amplifier used in their respective circuits.These commonly used delay cell topologies are adequate for frequenciesunder 1 GHz, however, the VCOs used with these types of delay cells donot offer adequate frequency range when operating on or around 2.4 GHz.A VCO such as that shown in FIG. 3 will have a small to medium level oftuning range because of the limited resistive load variation set by themetal oxide semiconductor field effect transistor (MOSFET) operating inthe triode region. By way of example, U.S. Pat. No. 6,011,443 shows acomplementary metal oxide semiconductor (CMOS) VCO that includes avoltage-to-current converter for generating reference currents. Thistype of circuit causes each of the load metal oxide semiconductor (MOS)transistors to operate in the triode region and suffers from all of theinherent drawbacks mentioned herein. Moreover, tank oscillators whichrequire an inductor and capacitor to oscillate (LC type) take up largeamounts of circuit area when implemented with current integrated circuit(IC) technology, and generally require additional processing stepsduring the manufacturing process.

Thus, the need exists to provide a new circuit topology for a highfrequency VCO using delay cells operable at frequencies in the WPAN IEEE802.15.4 standard. The new invention should be capable of beingimplemented in an all CMOS technology operable on or about 2.4 GHz. Thedevice should use no internal or external inductors that would requireadditional cost and IC surface area. Moreover, the VCO should be capableof tuning over all process, temperature, and supply voltage corners suchthat its operational voltage remains within a few decibels (dB) of anominal value.

SUMMARY OF THE INVENTION

Briefly, according to the invention, there is provided a two port ringoscillator type VCO that uses delay cells to operate nominally atapproximately 2.4 GHz in a WPAN or other high frequency networking RFsystem. In a ring oscillator, the delay cells operate to cause a phaseshift in the signal and, if sufficiently large, causes the ringoscillator to oscillate. The invention includes presenting the delaycells with a non-linear dynamic load which improves the center frequencyby approximately 30-40 percent while maintaining substantially the samecurrent drain and sideband noise specification. In addition, metal oxidesemiconductor field effect transistors (MOSFETs) can be used to controlthe center frequency and tuning sensitivity (K_(v)) over process,temperature, and supply voltage.

The use of multi-biased MOSFETs helps to reduce the non-linearity inK_(v) curves versus tuning voltage. In that inductors are not used inthe VCO, the center frequency will vary approximately 20 percent moreover process as compared with a typical inductor-capacitor (LC) typering VCO. This increases the coarse tuning of the center frequency overa substantially larger range than an LC type oscillator. This isaccomplished not only through tuning and programming MOSFET caps, butalso by using successive VCOs on the same die with differently designedcenter frequencies. Consequently, switching times between the VCOsduring coarse tune is critical in that the coarse tune will incrementthrough successive ring oscillators and must be very quick. Hence, theinvention further includes bypassing the filter between the bias and VCOwith a MOSFET switch in order for the time constant of the turn-off andon of the VCO from becoming unacceptably large. The filter as describedherein is essential to maintaining low sideband noise in the VCO forpreventing the bias circuitry from dominating the sideband noise. It isthe combination of these novel techniques which enables a low-cost,highly-integrated, all-complementary, metal oxide semiconductor (CMOS)WPAN VCO for use at frequencies above 1 GHz.

BRIEF DESCRIPTION OF THE DRAWINGS

The features of the present invention, which are believed to be novel,are set forth with particularly in the appended claims. The invention,together with further objects and advantages thereof, may best beunderstood by reference to the following description, taken inconjunction with the accompanying drawings, in the several figures ofwhich like reference numerals identify like elements, and in which:

FIG. 1 is a prior art block diagram of a ring oscillator type VCOincluding a series of delay cells.

FIG. 2 is a prior art circuit diagram of a current starved ringoscillator delay cell.

FIG. 3 is a prior art circuit diagram of a non-linear resister-capacitor(RC) type ring oscillator delay cell.

FIG. 4 is a block diagram of a two port VCO using a delay cell for usewith a UHF WPAN synthesizer according to the preferred embodiment of theinvention.

FIG. 5 is a circuit diagram for the two port VCO as shown in FIG. 4.

FIG. 6 is a detailed circuit diagram of a composite voltage variablecapacitor (VVC) load as used in the preferred embodiment of theinvention.

FIG. 7 is a graphical diagram illustrating the effect of staggering ofthe bias on multiple VVCs for producing a ‘composite’ VVC with a widerrange.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

While the specification concludes with claims defining the features ofthe invention that are regarded as novel it is believed that theinvention will be better understood from a consideration of thefollowing description in conjunction with the drawing figures, in whichlike reference numerals are carried forward.

Referring now to FIG. 4, a two port voltage controlled oscillator usinga delay cell operable with a high frequency wireless personal areanetwork (WPAN) synthesizer includes a current amplifier 101 thatreceives an input current at input I_(IN). Since it is necessary toadjust each delay cell 100 for a predetermined amount of delay and gainin order to maintain oscillation of the VCO, a variableresister-capacitor (RC) circuit 103 is used before the current isdirected to output I_(OUT). As discussed herein, the variable RC circuit103 includes a plurality of resistors and capacitors in order to adjustboth gain and delay of the delay cell 100 in order to provide optimumoperation of the VCO above approximately 1 GHz. In order to ensure thatthe delay cell 100 operates with low noise, the biasing network 105includes a filter network 107 that acts to eliminate circuit noise thatmight enter the current amplifier 101. In order that the variable RCcircuit 103 of the delay cell might be tuned more quickly, a switch 109is provided so that the filter network 107 may be selectively bypassed.As will be evident to those skilled in the art, during the tuning modeit is not necessary for the VCO to operate in a low noise mode.Therefore, the filter network 107 may be bypassed enabling the VCO to bemore rapidly tuned.

FIG. 5 illustrates the circuit topology of the VCO as seen in FIG. 4. Adifferential input current is presented to the input as I_(IN) such thatI_(IN)=I_(IN) ⁺−I_(IN) ⁻ where the input amount is amplified using afirst gain stage comprised of FETs 201, 203, 213 and 215. A supplyvoltage (V_(CC)) supplies voltage to the first gain stage which isconfigured like a current mirror only with the source of each pairconnected at a common point such as a differential pair. Thedifferential current is amplified by the ratio M which is set by theratio of width over length of pairs 201 and 203, and 215 and 213. Theoutput appears as a differential voltage, V_(OUT), across both the loadand capacitors 211, 207 and 209. One means used to control theamplification of the first gain stage includes a first variable resistor205 which controls signal applied to the common-gate input of the FET201. The output of the first gain stage is then applied to a variable Ccircuit that is used to control the amount of delay and gain. Thevariable input resistors 205, 217 and variable capacitors 211, 207, and209 then form the RC circuit which give the VCO the ability to vary thegain and delay. The variable RC circuit includes variable capacitors207, 209 that are used for fine tuning the amount of delay in additionto a variable capacitor 211 used for coarse tuning the amount of delay.The variable capacitors may be configured as shown in FIG. 6 describedherein.

As noted in FIG. 4, a biasing network 219 is used in connection with afilter 221 to provide a clean analog bias signal to control the gate ofFET 225. A switch 223 is used to bypass the filter network 221 whenadjusting tuning delay in order to enable the delay to be adjusted at afaster rate. Although the topology described herein is depicted withFETs, those skilled in the art will recognize that other semiconductordevices such as bipolar transistors may operate in a similarconfiguration as well.

FIG. 6 illustrates a circuit topology of a composite voltage variablecapacitance (VVC) 300 portion of the RC load. As noted above, thisdescription may be applied to the variable capacitors 207 and 209 fromFIG. 5. Differential nodes 301 and 303 comprise the differential load tothe differential pair of FET transistors 203 and 213 as described inFIG. 5. The tuning control voltage node 325 corresponds to the V_(TUNE)node between variable capacitors 207 and 209 as also seen in FIG. 5.Node 325 connects to the common connection of voltage variablecapacitors (VVCs) 305 and 309. The opposite connections of VVCs 305 and309 connect through biasing resistors to a common first bias reference321.

The biasing resistors allow one set of biasing conditions to beestablished across VVCs 305 and 309 to create a single bias dependentcapacitance loading curve that may be defined as the capacitance betweenthe differential load nodes 301 and 303. Additional alternating current(AC) coupling capacitors 313 and 317 prevent the biasing resistors fromappearing as a direct current (DC) load on nodes 301 and 303 as well aspreventing biasing conditions on nodes 301 and 303 from affecting thecapacitance loading curves of VVCs 305 and 309. Node 325 furtherconnects to the common connection of VVCs 307 and 311. The oppositeconnections of VVCs 307 and 311 connect through biasing resistors to acommon second bias reference 323. The biasing resistors allow a secondset of biasing conditions to be established across VVCs 307 and 311 tocreate a second bias dependent capacitance loading curve as definedbetween the differential load nodes 301 and 303. AC coupling capacitors315 and 319 prevent the biasing resistors from appearing as a DC load onnodes 301 and 303 as well as preventing the biasing conditions on nodes301 and 303 from affecting the capacitance loading curves of VVCs 307and 311. As will be further evident to those skilled in the art,additional stages may be added in a similar manner as needed to provideadditional capacitance.

FIG. 7 illustrates an idealized graphical representation using anapproach where the bias references may be staggered to provide a wideroverall “composite” capacitance loading curve than a load provided by anindividual VVC. This is known as a composite voltage variablecapacitance (CVVC). Curve 401 represents the capacitance loading thatmay be traced between differential nodes 301 and 303 in FIG. 6 bysweeping the tuning control voltage on node 325 working against thefirst bias reference if only VVCs 305 and 309 were connected betweennodes 301 and 303 through AC coupling capacitances 313 and 317.Similarly, curve 403 represents the capacitance loading that would betraced between nodes 301 and 303 in FIG. 6. This is accomplished bysweeping the tuning control voltage on node 325 working against thesecond bias reference only if VVCs 307 and 311 are connected betweennodes 301 and 303 through AC coupling capacitors 315 and 319. Using anappropriate choice of reference biases and using both sets of AC coupledVVCs together which presents a load to the delay cell at the same time,a condition can be created allowing the VVCs 307 and 311 to start theirload curve change just as the VVCs 305 and 309 are coming to the end oftheir load curve change. This has the desirable effect of extending thetotal tune control voltage range over which the load curve is changingas demonstrated by curve 405. The combination of both pairs of VVCs,i.e., VVCs 305, 309 in conjunction with VVCs 307, 311, creates theloading effect of a single composite VVC with a much wider range.Additional VVC pairs can be added in a similar manner as needed toextend a greater range of capacitance. Indeed, VVCs can be combined inthis same manner to provide a variety of loading curve shapes to meetdemanding performance requirements.

Thus, in summary, the present invention provides a two port VCO thatuses a delay cell and current amplifiers for amplifying an inputcurrent. One or more variable RC filters are used for varying the amountof signal delay in the VCO. The invention provides many improvementsover the prior art delay cell devices including a unique VVCconfiguration to enable a manufacturable VCO to operate in a stablemanner at frequencies above 1 GHz.

While the preferred embodiments of the invention have been illustratedand described, it will be clear that the invention is not so limited.Numerous modifications, changes, variations, substitutions andequivalents will occur to those skilled in the art without departingfrom the spirit and scope of the present invention as defined by theappended claims.

1. A voltage controlled oscillator (VCO) comprising: at least onecurrent amplifier for amplifying an input current; and a variableresister capacitor (RC) filter for varying the amount of signal delay inthe VCO.
 2. A VCO as in claim 1, further comprising: a filter forremoving unwanted signal components from a biasing network.
 3. A VCO asin claim 2, wherein the filter is capable of being bypassed using atleast one switch.
 4. A VCO as in claim 1, wherein the variable RC filterincludes at least one variable capacitor for fine tuning the amount ofsignal delay in the VCO.
 5. A VCO as in claim 1, wherein the variable RCfilter includes at least one variable capacitor for coarse tuning theamount of signal delay.
 6. A VCO as in claim 1, wherein the RC filterincludes a composite voltage variable capacitor (VVC) for enabling theRC filter to be finely tuned.
 7. A VCO as in claim 6, wherein thecomposite VVC utilizes a plurality of bias reference voltage and atleast one tuning control voltage for adjusting a precise capacitancevalue.
 8. A voltage controlled oscillator (VCO) including a current modedelay cell comprising: a first current amplifier for amplifying an inputcurrent; a resister capacitor (RC) tuning network for varying the amountof amplification and delay of an output of the first current amplifier;and a second current amplifier for amplifying an output current from theRC tuning network.
 9. A VCO as in claim 8, wherein the RC tuning networkincludes at least one variable resistor for controlling the gain of thefirst current amplifier and second current amplifier.
 10. A VCO as inclaim 8, wherein the RC tuning network includes at least one variablecapacitor for fine tuning the amount of signal delay in the delay cell.11. A VCO as in claim 8, wherein the RC tuning network includes at leastone variable capacitor for coarse tuning the amount of signal delay inthe delay cell.
 12. A VCO as in claim 8, further comprising at least onefilter for providing a low noise bias voltage from at least one biassupply.
 13. A VCO as in claim 12, wherein the at least one filter iscapable of being switchably bypassed from at least one bias supply. 14.A VCO as in claim 8, wherein the RC tuning network includes a compositevoltage variable capacitor (VVC) for enabling the RC filter to be finelytuned.
 15. A VCO as in claim 14, wherein the composite VVC utilizes aplurality of bias reference voltage and at least one tuning controlvoltage for adjusting the capacitance value.
 16. A method for providingsignal delay in a voltage controlled oscillator (VCO) using a delay cellcomprising the steps of: amplifying an input current with at least onecurrent amplifier; and adjusting the amount of signal delay from the atleast one current amplifier using a delay network.
 17. A method forproviding signal delay in a VCO as in claim 16, wherein the delaynetwork includes at least one variable resistor and at least onevariable capacitor for providing adjustable signal delay.
 18. A methodfor providing signal delay in a VCO as in claim 16, wherein the at leastone current amplifier includes a first current amplifier at an input ofthe VCO delay cell and a second current amplifier at an output of theVCO delay cell.
 19. A method for providing signal delay in a VCO as inclaim 16, further comprising the step of: providing a bias to the VCOdelay cell using a switchable filter that is capable of being bypassed.20. A method for providing signal delay in a VCO as in claim 16, furthercomprising the step of: coarse tuning the amount of signal delay in theVCO delay cell using at least one variable resister.
 21. A method forproviding signal delay in a VCO as in claim 16, further comprising thestep of: fine tuning the amount of signal delay using at least onevariable capacitor.
 22. A method for providing signal delay as in claim16, wherein the step of adjusting includes: tuning a resister capacitor(RC) network using a composite voltage variable capacitor (VVC) for finetuning the amount of signal delay.
 23. A method for providing signaldelay as in claim 22, wherein the composite VVC utilizes a plurality ofbias reference voltages and at least one tuning control voltage foradjusting the capacitance value.